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Data Sheet
ADE7880
Bit
8:6
Mnemonic
CF3SEL[2:0]
Default Value
010
Description
000: the CF3 frequency is proportional to the sum of total active powers on
each phase identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register.
010: the CF3 frequency is proportional to the sum of apparent powers on
each phase identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register.
011: CF3 frequency is proportional to the sum of fundamental active powers
on each phase identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE
register.
100: CF3 frequency is proportional to the sum of fundamental reactive
powers on each phase identified by Bits[8:6] (TERMSEL3[x]) in the
COMPMODE register.
001, 101,110,111: reserved.
9
CF1DIS
1
When this bit is set to 1, the CF1 output is disabled. The respective digital to
frequency converter remains enabled even if CF1DIS = 1.
When this bit is set to 0, the CF1 output is enabled.
10
CF2DIS
1
When this bit is set to 1, the CF2 output is disabled. The respective digital to
frequency converter remains enabled even if CF2DIS = 1.
When this bit is set to 0, the CF2 output is enabled.
11
CF3DIS
1
When this bit is set to 1, the CF3 output is disabled. The respective digital to
frequency converter remains enabled even if CF3DIS = 1.
When this bit is set to 0, the CF3 output is enabled.
12
CF1LATCH
0
When this bit is set to 1, the content of the corresponding energy registers is
latched when a CF1 pulse is generated. See the Synchronizing Energy
Registers with CFx Outputs section.
13
CF2LATCH
0
When this bit is set to 1, the content of the corresponding energy registers is
latched when a CF2 pulse is generated. See the Synchronizing Energy
Registers with CFx Outputs section.
14
CF3LATCH
0
When this bit is set to 1, the content of the corresponding energy registers is
latched when a CF3 pulse is generated. See the Synchronizing Energy
Registers with CFx Outputs section.
15
Reserved
0
Reserved. This bit does not manage any functionality.
Table 45. APHCAL, BPHCAL, CPHCAL Registers (Address 0xE614, Address 0xE615, Address 0xE616)
Bit
9:0
Mnemonic
PHCALVAL
Default Value
0000000000
Description
If current channel compensation is necessary, these bits can vary only between 0 and 383.
If voltage channel compensation is necessary, these bits can vary only between 512 and 575.
If the PHCALVAL bits are set with numbers between 384 and 511, the compensation behaves
like PHCALVAL set between 256 and 383.
If the PHCALVAL bits are set with numbers between 576 and 1023, the compensation
behaves like PHCALVAL bits set between 384 and 511.
15:10
Reserved
000000
Reserved. These bits do not manage any functionality.
Table 46. PHSIGN Register (Address 0xE617)
Bit
0
Mnemonic
AWSIGN
Default Value
0
Description
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase A is positive.
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase A is negative.
1
BWSIGN
0
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase B is positive.
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase B is negative.
2
CWSIGN
0
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase C is positive.
1: if the active power identified by Bit 6 (REVAPSEL) bit in the ACCMODE register (total of
fundamental) on Phase C is negative.
Rev. A| Page 97 of 104
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